The invention relates to a memory device having an array of memory cells such as DRAM (Dynamic Random Access Memory) cells, as well as to a method of manufacturing such a memory device.
Memory cells of a dynamic random access memory (DRAM) generally include a storage capacitor for storing an electrical charge that represents an information to be stored and an access transistor which is connected with a storage capacitor. The access transistor includes a first and a second source/drain region, a channel connecting the first and the second source/drain region as well as a gate electrode controlling an electrical current flow between the first and the second source/drain region. The transistor usually is at least partially formed in the semiconductor substrate. The gate electrode forms part of the word line and is electrically insulated from the channel by a gate dielectric. By addressing the access transistor via a corresponding word line, the information stored in the storage capacitor is read out to a corresponding bit line.
In the currently used DRAM memory cells, the storage capacitor can be implemented as a trench capacitor in which the two capacitor electrodes are disposed in a trench that extends in the substrate in a direction perpendicular to the substrate surface.
In one implementation of the DRAM memory cell, the electrical charge is stored in a stacked capacitor, which is formed above the surface of the substrate.
FIG. 28 illustrates an exemplary plan view of a memory device, having a memory cell array II and a peripheral portion I. A boundary region III is formed between the memory cell array II and the peripheral portion I. The memory cell array II includes a plurality of memory cells 330, each of the memory cells have a storage capacitor 24 and an access transistor 30. The storage capacitor includes a first and a second capacitor electrode 17, 19, the first capacitor electrode 17 being connected with a first source/drain region 31 of the access transistor. The channel 33 is formed between the first and the second source/drain region 31, 32 and a gate electrode 34 controls the conductivity of the channel 33. The gate electrode 34 is insulated from the channel 33 by a gate insulating layer 35. By addressing the address transistor 30 via the corresponding word line 310, the information stored in the storage capacitor is read out to a corresponding bit line 320. The layout illustrated in FIG. 28 corresponds to the so-called folded bit line layout. However, as is to be clearly understood, the present invention is applicable to any kind of memory cell array layouts.
The support portion I refers to a portion at the edge of the memory cell array in which support circuits such as decoders, sense amplifiers 340 and word line drivers 350 for activating a word line 310 are located. Generally, the peripheral portion of a memory device includes circuitry for addressing memory cells and for sensing and processing the signals received from the individual memory cells. Usually, the peripheral portion is formed in the same semiconductor substrate as the individual memory cells. In addition, the boundary region is as well formed in the same semiconductor substrate. Hence, it is highly desirable to have a manufacturing process by which the components of the memory cell array and the peripheral portion can be formed simultaneously.
In particular, if the storage capacitor of the memory cell is implemented as a stacked capacitor extending above the semiconductor substrate surface, a problem arises that the whole substrate surface is covered by a thick sacrificial layer which is removed during the processing of the stacked capacitor. After completion of the capacitor, a second deposition step of a dielectric layer has to be made in order to provide an insulation for the following metal layer.
A further problem arises, that during the processing of the peripheral portion a contact for contacting the peripheral portion has to be formed by etching a contact hole through a thick layer (3 μm) of an insulating material.
U.S. Pat. No. 5,895,239 discloses a method of forming a memory device in which bit lines in the array portion are formed simultaneously with landing plugs in the peripheral portion. In particular, according to this patent, the landing plugs are formed at a level of the first wiring layer.